Placement-aware Hardware Description Languages


This project aims to develop hardware description languages for expressing spatially parallel hardware.


Professor Philip Leong, Associate Professor Craig Jin, Professor Alistair McEwan

Research Location

Electrical and Information Engineering

Program Type



FPGA designs have very fast internal components but achievable clock rates for most designs are modest. In this work, methods for automatically generating highly pipelined designs with spatial locality so clock frequency can be maximised will be studied.  We will begin by developing hand-optimised designs of blocks such as correlators, filters and floating point units and then develop tools which can derive the same design from a high level description.  Ultimately, a high level programming language for FPGA devices in which both placement and computation can be described will be developed.

Want to find out more?

Contact us to find out what’s involved in applying for a PhD. Domestic students and International students

Contact Research Expert to find out more about participating in this opportunity.

Browse for other opportunities within the Electrical and Information Engineering .


FPGA, reconfigurable computing, parallelism, hardware description language, behavioural synthesis

Opportunity ID

The opportunity ID for this research opportunity is: 1060

Other opportunities with Professor Philip Leong

Other opportunities with Associate Professor Craig Jin

Other opportunities with Professor Alistair McEwan