Outline

Overview

The purpose of this unit is to equip students with the skills to design simple digital logic circuits which comprise modules of larger digital systems. The following topics are covered: logic operations, theorems and Boolean algebra, number systems (integer and floating point), combinational logic analysis and synthesis, sequential logic, registers, counters, bus systems, state machines, simple CAD tools for logic design, and the design of a simple computer.

Unit details and rules

Academic unit	School of Electrical and Computer Engineering
Credit points	6
Prerequisites ?	None
Corequisites ?	None
Prohibitions ?	None
Assumed knowledge ?	ELEC1601. This unit of study assumes some knowledge of digital data representation and basic computer organisation
Available to study abroad and exchange students	Yes

Teaching staff

Coordinator	David Boland, david.boland@sydney.edu.au

Assessment

The census date for this unit availability is 31 March 2026

Details
Criteria

Type	Description	Weight	Due	Length	Use of AI
Written exam	Final exam Final Exam	40%	Formal exam period	2 hours	AI prohibited
Outcomes assessed:
Q&A following presentation, submission or placement	Lab exercises (Essential) Completion of 4 Lab Exercises in groups. You must demonstrate your code works and be able to discuss questions from your demonstrators. AI allowed in implementation, but must be able to explain it without AI	16%	Multiple weeks	n/a	AI limited - refer to Canvas
Outcomes assessed:
Practical skill	Setup Home Simulation on home PC Must demonstrate this in labs. #earlyfeedbacktask	0%	Week 02	1 hour	AI allowed
Outcomes assessed:
Interactive oral	Basic combinational logic design in Verilog in Lab Must show basic skills before joining a group. Lab demonstrator will test your understanding orally. AI allowed in implementation, but must be able to explain it without AI	4%	Week 03	30 minutes	AI limited - refer to Canvas
Outcomes assessed:
In-class quiz	Combinational Logic Quiz Canvas Quiz. Taken in tutorials. 80% to pass. AI allowed in preparation, but not in assessment	7%	Week 06	30 Minutes	AI allowed
Outcomes assessed:
Interactive oral	FSM design quiz Taken during tutorial session. Oral discussion about how to design an FSM and implement it in Verilog. AI allowed in implementation, but must be able to explain it without AI	6%	Week 11	30 Minutes	AI limited - refer to Canvas
Outcomes assessed:
In-class quiz	Sequential Logic Quiz Canvas Quiz.Taken in tutorials. 80% to pass. AI allowed in preparation, but not in assessment	7%	Week 11	30 minutes	AI allowed
Outcomes assessed:
Q&A following presentation, submission or placement	Project Project demonstration. Demonstrators will check understanding and contribution with oral assessment. There will be "essential criteria" - hurdle for 10% and 10% for advanced designs AI allowed in implementation, but must be able to explain it without AI	20%	Week 13	N/A	AI limited - refer to Canvas
Outcomes assessed:
= hurdle task ? = group assignment ? = early feedback task ?

Early feedback task

This unit includes an early feedback task, designed to give you feedback prior to the census date for this unit. Details are provided in the Canvas site and your result will be recorded in your Marks page. It is important that you actively engage with this task so that the University can support you to be successful in this unit.

Assessment summary

This course shares aspects of the assessment structure of ELEC1601. However, the exam has greater weight in this course.

Essential (50%):
- Quizzes (Individual, completed during a lab session):
  - Must score 80% or more on 3 quizzes.
    - Short Canvas Quiz on Logic Gates/Simplification.
    - Short Canvas Quiz on Flip-flops, Registers, Simple Datapaths.
    - Short Interactive oral quiz on FSM design
  - Lab tests (individual):
    - Basic combinational logic design in Verilog
  - Lab Completion (team of 3):
    - Exercises 2-5 only available after passing basic lab test, completed as a group, assessed orally
  - Project:
    - Implementation of basic processor (as described in lecture) working in Simulation

Project extension (10%):
- Project extension goals met (TBC. Examples include):
  - 16 8-bit registers
  - Custom instructions
  - Load/Store from memory
  - Using a program counter.
  - High-frequency design,
  - Parallelism,
  - Complex custom instructions
Exam (40%)
- Will have short section to test aspects on quizzes in formal test environment (worth 5%, pass/fail).
- Rest will be designed for D/HD student

Assessment criteria

The University awards common result grades, set out in the Coursework Policy 2014 (Schedule 1).

As a general guide, a high distinction indicates work of an exceptional standard, a distinction a very high standard, a credit a good standard, and a pass an acceptable standard.

Result name	Mark range	Description
High distinction	85 - 100	Able to demonstrate deep knowledge of advanced material
Distinction	75 - 84	Able to demonstrate deeper knowledge of extension material
Credit	65 - 74	Meet essential criteria and some extension material
Pass	50 - 64	Meet essential Criteria
Fail	0 - 49	When you don’t meet the learning outcomes of the unit to a satisfactory standard.

For more information see guide to grades.

Use of generative artificial intelligence (AI)

You can use generative AI tools for open assessments. Restrictions on AI use apply to secure, supervised assessments used to confirm if students have met specific learning outcomes.

Refer to the assessment table above to see if AI is allowed, for assessments in this unit and check Canvas for full instructions on assessment tasks and AI use.

If you use AI, you must always acknowledge it. Misusing AI may lead to a breach of the Academic Integrity Policy.

Visit the Current Students website for more information on AI in assessments, including details on how to acknowledge its use.

Late submission

In accordance with University policy, these penalties apply when written work is submitted after 11:59pm on the due date:

Deduction of 5% of the maximum mark for each calendar day after the due date.
After ten calendar days late, a mark of zero will be awarded.

Academic integrity

The University expects students to act ethically and honestly and will treat all allegations of academic integrity breaches seriously.

Our website provides information on academic integrity and the resources available to all students. This includes advice on how to avoid common breaches of academic integrity. Ensure that you have completed the Academic Honesty Education Module (AHEM) which is mandatory for all commencing coursework students

Penalties for serious breaches can significantly impact your studies and your career after graduation. It is important that you speak with your unit coordinator if you need help with completing assessments.

Visit the Current Students website for more information on AI in assessments, including details on how to acknowledge its use.

Learning support

Simple extensions

If you encounter a problem submitting your work on time, you may be able to apply for an extension of five calendar days through a simple extension.  The application process will be different depending on the type of assessment and extensions cannot be granted for some assessment types like exams.

Special consideration

If exceptional circumstances mean you can’t complete an assessment, you need consideration for a longer period of time, or if you have essential commitments which impact your performance in an assessment, you may be eligible for special consideration or special arrangements.

Special consideration applications will not be affected by a simple extension application.

Using AI responsibly

Co-created with students, AI in Education includes lots of helpful examples of how students use generative AI tools to support their learning. It explains how generative AI works, the different tools available and how to use them responsibly and productively.

Support for students

The Support for Students Policy reflects the University’s commitment to supporting students in their academic journey and making the University safe for students. It is important that you read and understand this policy so that you are familiar with the range of support services available to you and understand how to engage with them.

The University uses email as its primary source of communication with students who need support under the Support for Students Policy. Make sure you check your University email regularly and respond to any communications received from the University.

Learning resources and detailed information about weekly assessment and learning activities can be accessed via Canvas. It is essential that you visit your unit of study Canvas site to ensure you are up to date with all of your tasks.

If you are having difficulties completing your studies, or are feeling unsure about your progress, we are here to help. You can access the support services offered by the University at any time:

Support and Services (including health and wellbeing services, financial support and learning support)
Course planning and administration
Meet with an Academic Adviser

Weekly schedule

WK	Topic	Learning activity
Multiple weeks	Total of 9 - 12 hours per week commitment is expected for a typical 6 cp unit. 1-hour tutorial plus 3-hour lab plus 2-hour lecture leaves 3-6 hours per week.	Self-directed learning (72 hr)
Week 01	Introduction to digital logic	Lecture (2 hr)
Week 02	Verilog and simulation introduction.	Lecture (2 hr)
Week 02	Software installation and basic verilog	Practical (3 hr)
Week 03	Boolean Algebra, Canonical Forms	Lecture (2 hr)
	Verilog Structural/Combinational discussion for Quiz	Tutorial (1 hr)
	Lab 1 (plus test) - Basic combinational designs	Practical (3 hr)
Week 04	Sum of Product and Product of Sums to understand circuits. Lab 2 discussion	Lecture (2 hr)
	Boolean Algebra/Canonical Forms for Quiz	Tutorial (1 hr)
	Lab 2 - Simple Datapaths, Multiplexers on FPGAs	Practical (3 hr)
Week 05	Logic simplification. Lab 3 discussion	Lecture (2 hr)
	Boolean Simplification for Quiz, Practice Assessment	Tutorial (1 hr)
	Lab 3 – Structural design for larger combinational datapaths on FPGAs	Practical (3 hr)
Week 06	Memory, Lab 4 discussion.	Lecture (2 hr)
	Quiz (assessment). Combinational logic design	Tutorial (1 hr)
	Lab 4 - More combinational design practice	Practical (3 hr)
Week 07	Registers and Timing	Lecture (2 hr)
	Catch-up and Retakes	Tutorial (1 hr)
	Catch-up and complete	Practical (3 hr)
Week 08	FSMs, Lab 5 discussion	Lecture (2 hr)
	Timing understanding for quiz	Tutorial (1 hr)
	Lab 5 - FSMs	Practical (3 hr)
Week 09	Processors, project discussion	Lecture (2 hr)
	Basic Timing - Max clock frequency. Understanding FSMs	Tutorial (1 hr)
	Catch-up	Practical (3 hr)
Week 10	Processors – busses and control logic	Lecture (2 hr)
	FSM Design (for project and quiz)	Tutorial (1 hr)
	Project	Practical (3 hr)
Week 11	Processors – Memory	Lecture (2 hr)
	Quiz (assessment). Sequential logic design and FSM design	Tutorial (1 hr)
	Project	Practical (3 hr)
Week 12	Extension memory/timing/metastability	Lecture (2 hr)
	Catch-up/Project Assistance	Tutorial (1 hr)
	Project	Practical (3 hr)
Week 13	Revision	Lecture (2 hr)
	Catch-up/Project Assistance	Tutorial (1 hr)
	Project Demo and Marking	Practical (3 hr)

Study commitment

Typically, there is a minimum expectation of 1.5-2 hours of student effort per week per credit point for units of study offered over a full semester. For a 6 credit point unit, this equates to roughly 120-150 hours of student effort in total.

Required readings

All readings for this unit can be accessed on the Library eReserve link available on Canvas.

Fundamentals of Digital Logic with Verilog Design, Stephen Brown and Zvonko Vranesic, 3rd edition, McGraw-Hill, 2009

Learning outcomes

Learning outcomes are what students know, understand and are able to do on completion of a unit of study. They are aligned with the University's graduate qualities and are assessed as part of the curriculum.

Outcomes
Graduate qualities

At the completion of this unit, you should be able to:

LO1. Understand how Boolean Algebra can be used for the purpose of logic circuit analysis and optimization
LO2. Understand and utilise basic combinational logic building blocks such as logic gates, multiplexers and decoders.
LO3. Understand and utilise basic sequential logic components such as latches, registers and memory.
LO4. Design digital circuits building upon basic combinational and sequential components, using a clearly defined system based approach.
LO5. Evaluate the performance of clocked sequential circuits
LO6. Design and test the digital systems using FPGAs
LO7. Communicate effectively among the team members of the group.

Graduate qualities

The graduate qualities are the qualities and skills that all University of Sydney graduates must demonstrate on successful completion of an award course. As a future Sydney graduate, the set of qualities have been designed to equip you for the contemporary world.

GQ1	Depth of disciplinary expertise Deep disciplinary expertise is the ability to integrate and rigorously apply knowledge, understanding and skills of a recognised discipline defined by scholarly activity, as well as familiarity with evolving practice of the discipline.
GQ2	Critical thinking and problem solving Critical thinking and problem solving are the questioning of ideas, evidence and assumptions in order to propose and evaluate hypotheses or alternative arguments before formulating a conclusion or a solution to an identified problem.
GQ3	Oral and written communication Effective communication, in both oral and written form, is the clear exchange of meaning in a manner that is appropriate to audience and context.
GQ4	Information and digital literacy Information and digital literacy is the ability to locate, interpret, evaluate, manage, adapt, integrate, create and convey information using appropriate resources, tools and strategies.
GQ5	Inventiveness Generating novel ideas and solutions.
GQ6	Cultural competence Cultural Competence is the ability to actively, ethically, respectfully, and successfully engage across and between cultures. In the Australian context, this includes and celebrates Aboriginal and Torres Strait Islander cultures, knowledge systems, and a mature understanding of contemporary issues.
GQ7	Interdisciplinary effectiveness Interdisciplinary effectiveness is the integration and synthesis of multiple viewpoints and practices, working effectively across disciplinary boundaries.
GQ8	Integrated professional, ethical, and personal identity An integrated professional, ethical and personal identity is understanding the interaction between one’s personal and professional selves in an ethical context.
GQ9	Influence Engaging others in a process, idea or vision.

Outcome map

Learning outcomes	Graduate qualities
Learning outcomes

Responding to student feedback

This section outlines changes made to this unit following staff and student reviews.

Refining structure to be more clear. Added tutorials to give students more time.

Disclaimer

Important: the University of Sydney regularly reviews units of study and reserves the right to change the units of study available annually. To stay up to date on available study options, including unit of study details and availability, refer to the relevant handbook.

To help you understand common terms that we use at the University, we offer an online glossary.

Current students

Overview

Overview

Unit details and rules

Teaching staff

Assessment

Assessment

Early feedback task

Assessment summary

Assessment criteria

Use of generative artificial intelligence (AI)

Late submission

Academic integrity

Learning support

Learning support

Simple extensions

Special consideration

Using AI responsibly

Support for students

Weekly schedule

Weekly schedule

Study commitment

Required readings

Learning outcomes

Learning outcomes

Graduate qualities

Outcome map

Responding to student feedback

Responding to student feedback

Disclaimer

On this page

Useful links

ELEC2602: Digital Logic

Semester 1, 2026 [Normal day] - Camperdown/Darlington, Sydney

Overview

Overview

Unit details and rules

Teaching staff

Assessment

Assessment

Early feedback task

Assessment summary

Assessment criteria

Use of generative artificial intelligence (AI)

Late submission

Academic integrity

Learning support

Learning support

Simple extensions

Special consideration

Using AI responsibly

Support for students

Weekly schedule

Weekly schedule

Study commitment

Required readings

Learning outcomes

Learning outcomes

Graduate qualities

Outcome map

Responding to student feedback

Responding to student feedback

Disclaimer

On this page

Useful links