Outline

Overview

The purpose of this unit is to equip students with the skills to design simple digital logic circuits which comprise modules of larger digital systems. The following topics are covered: logic operations, theorems and Boolean algebra, number systems (integer and floating point), combinational logic analysis and synthesis, sequential logic, registers, counters, bus systems, state machines, simple CAD tools for logic design, and the design of a simple computer.

Unit details and rules

Academic unit	School of Electrical and Computer Engineering
Credit points	6
Prerequisites ?	None
Corequisites ?	None
Prohibitions ?	ELEC5722
Assumed knowledge ?	This unit of study assumes some knowledge of digital data representation and basic computer organisation
Available to study abroad and exchange students	No

Teaching staff

Coordinator	David Boland, david.boland@sydney.edu.au
Lecturer(s)	David Boland, david.boland@sydney.edu.au

Assessment

The census date for this unit availability is 31 March 2025

Details
Criteria

Type	Description	Weight	Due	Length
Supervised exam ?	Final exam Verilog (modelsim/verilator) design activity based on labs/project.	35%	Formal exam period	2 hours
Outcomes assessed:
Small continuous assessment	Lab exercises (Essential) Completion of 4 group lab exercises.	15%	Multiple weeks	n/a
Outcomes assessed:
Small continuous assessment	Lab project (essential) Verilog design exercise as a group.	10%	Multiple weeks	n/a
Outcomes assessed:
Small continuous assessment	Lab exercises (extension) Complete remaining lab exercises.	8%	Multiple weeks	N.A
Outcomes assessed:
Online task	Setup Home Simulation on home PC Must demonstrate this in labs. EFT task	1%	Week 02	N/A
Outcomes assessed:
Small test	Combinational Logic Quiz Canvas Quiz. Taken in labs. 80% to pass	4%	Week 03	30 minutes
Outcomes assessed:
Small continuous assessment	Basic combinational logic design in Verilog Must show basic skills before joining a group	5%	Week 03	30 minutes
Outcomes assessed:
Small continuous assessment	Basic FSM implementation in Verilog Must show basic skills for FSM design (potentially gained in a group) have been developed individually	5%	Week 07	30 minutes
Outcomes assessed:
Small continuous assessment	FSM design quiz Canvas Quiz, handwritten answer. Taken in labs. Pass/Fail by demonstrator	5%	Week 09	30 Minutes
Outcomes assessed:
Assignment	Project Extension Complete additional tasks for project	4%	Week 13 Due date: 30 May 2025 at 23:59	N/A
Outcomes assessed:
Assignment	Project Advanced Complete additional tasks for project	3%	Week 13 Due date: 30 May 2025 at 23:59	N/A
Outcomes assessed:
Small test	Sequential Logic and Timing Quiz Canvas Quiz. Taken in labs. 80% to pass	5%	Week 13	30 minutes
Outcomes assessed:
= hurdle task ? = group assignment ? = AI allowed ? = early feedback task ?

Assessment summary

This course will follow a similar structure to ELEC1601 2024. As in ELEC1601, you can guarantee a pass before the exam.

However, the exam has greater weight in this course.

Essential (50%):
- Quizzes (Individual, completed during a lab session):
  - Must score 80% or more on 3 quizzes.

- - - Short Canvas Quiz on Logic Gates/Simplification.
      - Available Week 4 onwards
    - Short Canvas Quiz on Flip-flops, Registers, Simple Datapaths.
      - Available Week 6 onwards
    - Short Quiz on FSM design
      - Available Week 9 onwards
  - Lab tests (individual):
    - Basic combinational logic design in Verilog
      - Available Week 3 onwards
    - Basic FSM implementation in Verilog
      - Available Week 7 onwards
  - Lab Completion (team of 3):
    - Exercises 2-5 only available after passing basic lab test
    - Exercises 6 only available after passing FSM test
  - Project:
    - Implementation of basic processor (as described in lecture) working in Simulation
Extension (Up to 12%):
- Lab Completion (team of 3).
  - All exercises. Note these are designed to help you progress your understanding ready for the project.
- Project extension goals met (TBC):

- - 16 8-bit registers
  - Custom instructions
  - Load/Store from memory
  - Using a program counter.
Advanced (Up to 3%):
- Advanced Project:
  - Goals such as high-frequency design, parallelism, complex custom instructions,
Exam (35%)
- Will be designed for D/HD student

- - Student seeking a credit that has completed all extension material will require 5/35 (15%)
  - Student seeking a distinction that has completed all extension material will require 13/35 (37%)
  - Student seeking an HD that has completed extension and advanced material will require 20/35 (57%)

Assessment criteria

The University awards common result grades, set out in the Coursework Policy 2014 (Schedule 1).

As a general guide, a high distinction indicates work of an exceptional standard, a distinction a very high standard, a credit a good standard, and a pass an acceptable standard.

Result name	Mark range	Description
High distinction	85 - 100
Distinction	75 - 84
Credit	65 - 74
Pass	50 - 64
Fail	0 - 49	When you don’t meet the learning outcomes of the unit to a satisfactory standard.

For more information see guide to grades.

Use of generative artificial intelligence (AI) and automated writing tools

Except for supervised exams or in-semester tests, you may use generative AI and automated writing tools in assessments unless expressly prohibited by your unit coordinator.

For exams and in-semester tests, the use of AI and automated writing tools is not allowed unless expressly permitted in the assessment instructions.

The icons in the assessment table above indicate whether AI is allowed – whether full AI, or only some AI (the latter is referred to as “AI restricted”). If no icon is shown, AI use is not permitted at all for the task. Refer to Canvas for full instructions on assessment tasks for this unit.

Your final submission must be your own, original work. You must acknowledge any use of automated writing tools or generative AI, and any material generated that you include in your final submission must be properly referenced. You may be required to submit generative AI inputs and outputs that you used during your assessment process, or drafts of your original work. Inappropriate use of generative AI is considered a breach of the Academic Integrity Policy and penalties may apply.

The Current Students website provides information on artificial intelligence in assessments. For help on how to correctly acknowledge the use of AI, please refer to the  AI in Education Canvas site.

Late submission

In accordance with University policy, these penalties apply when written work is submitted after 11:59pm on the due date:

Deduction of 5% of the maximum mark for each calendar day after the due date.
After ten calendar days late, a mark of zero will be awarded.

Academic integrity

The Current Student website provides information on academic integrity and the resources available to all students. The University expects students and staff to act ethically and honestly and will treat all allegations of academic integrity breaches seriously.

We use similarity detection software to detect potential instances of plagiarism or other forms of academic integrity breach. If such matches indicate evidence of plagiarism or other forms of academic integrity breaches, your teacher is required to report your work for further investigation.

Learning support

Simple extensions

If you encounter a problem submitting your work on time, you may be able to apply for an extension of five calendar days through a simple extension.  The application process will be different depending on the type of assessment and extensions cannot be granted for some assessment types like exams.

Special consideration

If exceptional circumstances mean you can’t complete an assessment, you need consideration for a longer period of time, or if you have essential commitments which impact your performance in an assessment, you may be eligible for special consideration or special arrangements.

Special consideration applications will not be affected by a simple extension application.

Using AI responsibly

Co-created with students, AI in Education includes lots of helpful examples of how students use generative AI tools to support their learning. It explains how generative AI works, the different tools available and how to use them responsibly and productively.

Support for students

The Support for Students Policy reflects the University’s commitment to supporting students in their academic journey and making the University safe for students. It is important that you read and understand this policy so that you are familiar with the range of support services available to you and understand how to engage with them.

The University uses email as its primary source of communication with students who need support under the Support for Students Policy. Make sure you check your University email regularly and respond to any communications received from the University.

Learning resources and detailed information about weekly assessment and learning activities can be accessed via Canvas. It is essential that you visit your unit of study Canvas site to ensure you are up to date with all of your tasks.

If you are having difficulties completing your studies, or are feeling unsure about your progress, we are here to help. You can access the support services offered by the University at any time:

Support and Services (including health and wellbeing services, financial support and learning support)
Course planning and administration
Meet with an Academic Adviser

Weekly schedule

WK	Topic	Learning activity
Multiple weeks	Total of 9 - 12 hours per week commitment is expected for a typical 6 cp unit. 3-hour lab plus 2-hour lecture leaves 4-7 hours per week.	Independent study (72 hr)
Week 01	Introduction to digital logic	Lecture (2 hr)
Week 02	Verilog and implementing logic functions	Lecture and tutorial (5 hr)
Week 03	Combinational building blocks and Verilog	Lecture and tutorial (5 hr)
Week 04	Verilog building blocks, numbers and adders	Lecture and tutorial (5 hr)
Week 05	Comparators, adders and subtractors	Lecture and tutorial (5 hr)
Week 06	Flip-flops, latches and clocks	Lecture and tutorial (5 hr)
Week 07	Registers and counters	Lecture and tutorial (5 hr)
Week 08	Finite state machines	Lecture and tutorial (5 hr)
Week 09	Datapaths and control	Lecture and tutorial (5 hr)
Week 10	Processors, memory and branching	Lecture and tutorial (5 hr)
Week 11	Multipliers, dividers and timing	Lecture and tutorial (5 hr)
Week 12	Metastability and reconfigurable logic	Lecture and tutorial (5 hr)
Week 13	Synthesis, testing and exam review	Lecture and tutorial (5 hr)

Study commitment

Typically, there is a minimum expectation of 1.5-2 hours of student effort per week per credit point for units of study offered over a full semester. For a 6 credit point unit, this equates to roughly 120-150 hours of student effort in total.

Required readings

All readings for this unit can be accessed through the Library eReserve, available on Canvas.

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design (3rd). McGraw-Hill, 2009. 978-0-07-352953-0

Learning outcomes

Learning outcomes are what students know, understand and are able to do on completion of a unit of study. They are aligned with the University's graduate qualities and are assessed as part of the curriculum.

Outcomes
Graduate qualities

At the completion of this unit, you should be able to:

LO1. design, fabricate and test the digital circuits and system in the laboratory
LO2. design combinational and sequential circuits and systems, using a clearly defined system based approach
LO3. understand how Boolean Algebrea can be used for the purpose of logic circuit analysis
LO4. describe basic digital logic building blocks such as logic gates, multiplexers, decoders, and PLAs
LO5. discuss how sequential logic components such as latches, flip-flops, registers and counters work
LO6. evaluate the performance of clocked sequential circuits
LO7. communicate effectively among the team members of the group.

Graduate qualities

The graduate qualities are the qualities and skills that all University of Sydney graduates must demonstrate on successful completion of an award course. As a future Sydney graduate, the set of qualities have been designed to equip you for the contemporary world.

GQ1	Depth of disciplinary expertise Deep disciplinary expertise is the ability to integrate and rigorously apply knowledge, understanding and skills of a recognised discipline defined by scholarly activity, as well as familiarity with evolving practice of the discipline.
GQ2	Critical thinking and problem solving Critical thinking and problem solving are the questioning of ideas, evidence and assumptions in order to propose and evaluate hypotheses or alternative arguments before formulating a conclusion or a solution to an identified problem.
GQ3	Oral and written communication Effective communication, in both oral and written form, is the clear exchange of meaning in a manner that is appropriate to audience and context.
GQ4	Information and digital literacy Information and digital literacy is the ability to locate, interpret, evaluate, manage, adapt, integrate, create and convey information using appropriate resources, tools and strategies.
GQ5	Inventiveness Generating novel ideas and solutions.
GQ6	Cultural competence Cultural Competence is the ability to actively, ethically, respectfully, and successfully engage across and between cultures. In the Australian context, this includes and celebrates Aboriginal and Torres Strait Islander cultures, knowledge systems, and a mature understanding of contemporary issues.
GQ7	Interdisciplinary effectiveness Interdisciplinary effectiveness is the integration and synthesis of multiple viewpoints and practices, working effectively across disciplinary boundaries.
GQ8	Integrated professional, ethical, and personal identity An integrated professional, ethical and personal identity is understanding the interaction between one’s personal and professional selves in an ethical context.
GQ9	Influence Engaging others in a process, idea or vision.

Outcome map

Learning outcomes	Graduate qualities
Learning outcomes

Responding to student feedback

This section outlines changes made to this unit following staff and student reviews.

We are modifying the structure to be more like ELEC1601 to ensure individual students gain understanding. Modified structure will also allow for faster feedback

Disclaimer

The University reserves the right to amend units of study or no longer offer certain units, including where there are low enrolment numbers.

To help you understand common terms that we use at the University, we offer an online glossary.

Current students

Overview

Overview

Unit details and rules

Teaching staff

Assessment

Assessment

Assessment summary

Assessment criteria

Use of generative artificial intelligence (AI) and automated writing tools

Late submission

Academic integrity

Learning support

Learning support

Simple extensions

Special consideration

Using AI responsibly

Support for students

Weekly schedule

Weekly schedule

Study commitment

Required readings

Learning outcomes

Learning outcomes

Graduate qualities

Outcome map

Responding to student feedback

Responding to student feedback

Disclaimer

On this page

Useful links

ELEC9602: Digital Logic

Semester 1, 2025 [Normal day] - Camperdown/Darlington, Sydney

Overview

Overview

Unit details and rules

Teaching staff

Assessment

Assessment

Assessment summary

Assessment criteria

Use of generative artificial intelligence (AI) and automated writing tools

Late submission

Academic integrity

Learning support

Learning support

Simple extensions

Special consideration

Using AI responsibly

Support for students

Weekly schedule

Weekly schedule

Study commitment

Required readings

Learning outcomes

Learning outcomes

Graduate qualities

Outcome map

Responding to student feedback

Responding to student feedback

Disclaimer

On this page

Useful links