Outline

Overview

This unit of study aims to provide experience, confidence and competence in the design and implementation of embedded systems; to impart a detailed knowledge of the software and hardware architecture of modern embedded systems and an understanding of the use of these resources in product design; and to provide experience of working in a project team to design and prototype an embedded system. Content will include single processor systems, multiple and distributed processing systems, special purpose architectures (FPGA, DSPs etc) and their applications; embedded operating systems; standard interfacing of sensor and actuation systems; ADC/DAC, SSI, parallel, CAN bus etc.; specific requirements for embedded systems; problem definition and system design; tools for design, development and testing of prototype systems. The unit of study will include a project where groups of students design, develop and commission an embedded system product to meet a specification. At the end of this unit students will understand the organisation of single and multiple processor systems, special purpose architectures (FPGAs, DSPs etc.) and their applications. Students will have a detailed knowledge of the software and hardware architecture of a modern embedded system. This knowledge will include an in-depth understanding of the advantages and limitations of embedded processors, of the utilisation and interfacing of hardware resources, and of the design and development of software for embedded applications. The students will have the competence to develop and prototype embedded systems.

Unit details and rules

Unit code	MTRX3700
Academic unit	Aerospace, Mechanical and Mechatronic
Credit points	6
Prohibitions ?	MECH4710
Prerequisites ?	MTRX2700
Corequisites ?	None
Assumed knowledge ?	Completion of a first course in microprocessor systems, including assembly and C language programming, interfacing, introductory digital and analogue electronics
Available to study abroad and exchange students	Yes

Teaching staff

Coordinator	Viorela Ila, viorela.ila@sydney.edu.au
Lecturer(s)	Viorela Ila, viorela.ila@sydney.edu.au
Lecturer(s)	Yiduo Wang, yiduo.wang@sydney.edu.au
Tutor(s)	Lewis Watts, lwat0045@uni.sydney.edu.au
	Dechuan Liu, dechuan.liu@sydney.edu.au
	Derek Pin Jie Law, derek.law@sydney.edu.au

Type	Description	Weight	Due	Length
Supervised exam ?	Final Exam Open book	30%	Formal exam period	2 hours
Outcomes assessed:
Assignment	Assignment 2 Submission of video demonstration and report	10%	Mid-semester break Due date: 01 Oct 2023 at 23:59	3 weeks
Outcomes assessed:
Assignment	Assignment 3 Submission of video demonstration and report	5%	STUVAC Due date: 07 Nov 2023 at 23:59	1 week
Outcomes assessed:
Assignment	EDSTEM Lab 1 EDSTEM Lab	5%	Week 03 Due date: 15 Aug 2023 at 23:59	1 week
Outcomes assessed:
Assignment	EDSTEM Lab 2 EDSTEM Lab	5%	Week 04 Due date: 22 Aug 2023 at 23:59	1 week
Outcomes assessed:
Assignment	EDSTEM Lab 3 EDSTEM Lab	5%	Week 05 Due date: 29 Aug 2023 at 23:59	1 week
Outcomes assessed:
Assignment	Assignment 1 Submission of video demonstration and report	5%	Week 06 Due date: 10 Sep 2023 at 23:59	3 weeks
Outcomes assessed:
Assignment	EDSTEM Lab 4 EDSTEM Lab	5%	Week 06 Due date: 05 Sep 2023 at 23:59	1 weeks
Outcomes assessed:
Assignment	EDSTEM Lab 5 EDSTEM Lab	5%	Week 08 Due date: 19 Sep 2023 at 23:59	2 weeks
Outcomes assessed:
Presentation	Major Project - Pitch This is the pitch (5%) component of the Major Project	5%	Week 09 Due date: 05 Oct 2023 at 23:59	1 week
Outcomes assessed:
Creative assessment / demonstration	Major Project - Demo This is the Demo (10%) component of the Major Project	10%	Week 12 Due date: 26 Oct 2023 at 23:59	4 weeks
Outcomes assessed:
Assignment	Major Project - Report This is the report component of the major project	10%	Week 12 Due date: 29 Oct 2023 at 23:59	4 weeks
Outcomes assessed:
= hurdle task ? = group assignment ?

Assessment summary

Assessment Description

EDSTEM Labs 1-5: questions are to be answered individualy and will assess the progregress in understanding the course material.
Assignment 1: FPGA programming Students will be working in groups and is intended to ensure that all students gain practice in programming FPGA devices.
Assignemnt 2: FPGA Environment: Students will be working in groups to develop an FPGA programming project.
Assignemnt 3: FPGA Programming: Students will be working in groups to develop a System On Chip programming exercise.
Major Project: MTRX3700 Mechatronics 3 is a project-based unit of study. Students will work in larger groups of 5. There is strong emphasis placed on understanding the material so that a student can make things work in the lab. Most of the learning will therefore occur in the laboratory, and the assessment weighting of assignment and project work reflects this.
Demonstration: The major project will have a mandatory in-lab demonstration component during the last weeek of each assignment
Presentation: An oral presentation is required early in the Major Project development cycle and another presentation is required before demonstrating the results.
Moderation of Group Work Marks: Group marks for Lab Work will be moderated on the basis of individual effort and understanding, as perceived by the Lecturer and Tutor(s) and as self-reported by group members.
Must Pass Exams: To pass this unit of study it is necessary to obtain a mark of not less than 45% in the Examination component.
Detailed information for each assessment task can be found on Canvas.

Assessment Feedback

Students can expect feedback for this Unit of Study through discussion during lectures and laboratory sessions, through participation in the Ed discussion forum, and through written comments on assignments.
Students can provide feedback to the Lecturers and Tutors by discussion during lectures or tutorial/ laboratory sessions, and by submitting comments and questions to the Ed discussion forum.

Assessment criteria

The University awards common result grades as set out in the Coursework Policy 2014 (Schedule 1).

Standards Based Assessment

Final grades in this unit are awarded at levels of HD for High Distinction, DI for Distinction, CR for Credit, PS for Pass and FA for Fail as defined by University of Sydney Coursework Policy 2014.

As a general guide, a high distinction indicates work of an exceptional standard, a distinction a very high standard, a credit a good standard, and a pass an acceptable standard. For more information see sydney.edu.au/students/guide-to-grades.

For more information see guide to grades.

Late submission

In accordance with University policy, these penalties apply when written work is submitted after 11:59pm on the due date:

Deduction of 5% of the maximum mark for each calendar day after the due date.
After ten calendar days late, a mark of zero will be awarded.

Academic integrity

The Current Student website provides information on academic integrity and the resources available to all students. The University expects students and staff to act ethically and honestly and will treat all allegations of academic integrity breaches seriously.

We use similarity detection software to detect potential instances of plagiarism or other forms of academic integrity breach. If such matches indicate evidence of plagiarism or other forms of academic integrity breaches, your teacher is required to report your work for further investigation.

You may only use artificial intelligence and writing assistance tools in assessment tasks if you are permitted to by your unit coordinator, and if you do use them, you must also acknowledge this in your work, either in a footnote or an acknowledgement section.

Studiosity is permitted for postgraduate units unless otherwise indicated by the unit coordinator. The use of this service must be acknowledged in your submission.

Learning support

Simple extensions

If you encounter a problem submitting your work on time, you may be able to apply for an extension of five calendar days through a simple extension.  The application process will be different depending on the type of assessment and extensions cannot be granted for some assessment types like exams.

Special consideration

If exceptional circumstances mean you can’t complete an assessment, you need consideration for a longer period of time, or if you have essential commitments which impact your performance in an assessment, you may be eligible for special consideration or special arrangements.

Special consideration applications will not be affected by a simple extension application.

Using AI responsibly

Co-created with students, AI in Education includes lots of helpful examples of how students use generative AI tools to support their learning. It explains how generative AI works, the different tools available and how to use them responsibly and productively.

Weekly schedule

WK	Topic	Learning activity
Multiple weeks	Students are expected to commit to at least 5 hours per week of independent study in addition to timetabled activities.	Independent study (60 hr)
Week 01	Introduction to Digital Circuits and FPGA	Lecture (3 hr)
Week 01	Lab practice	Computer laboratory (3 hr)
Week 02	Introduction to Hardware description language	Lecture (3 hr)
Week 02	Lab practice	Computer laboratory (3 hr)
Week 03	Modular design in HDL	Lecture (3 hr)
Week 03	Lab practice	Computer laboratory (3 hr)
Week 04	FPGA design	Lecture (3 hr)
Week 04	Lab practice	Computer laboratory (3 hr)
Week 05	Communication protocols	Lecture (3 hr)
Week 05	FPGA programming	Computer laboratory (3 hr)
Week 06	Digital signal processing	Lecture (3 hr)
Week 06	FPGA programming	Computer laboratory (3 hr)
Week 07	Digital signal processing hardware	Lecture (3 hr)
Week 07	FPGA programming	Computer laboratory (3 hr)
Week 08	FPGA Design and Simulation	Lecture (2 hr)
Week 08	FPGA programming	Computer laboratory (3 hr)
Week 09	Group Work on Major Project	Computer laboratory (3 hr)
Week 10	Hardware/Software codesign	Lecture (2 hr)
Week 10	Group work on the Major Project	Project (3 hr)
Week 11	System Design, SoC, soft Processor	Lecture (2 hr)
Week 11	Group work on the Major Project	Project (3 hr)
Week 12	Major Project Evaluation	Project (3 hr)
Week 13	Overview	Lecture (2 hr)
Week 13	FPGA laboratory	Project (3 hr)

Study commitment

Typically, there is a minimum expectation of 1.5-2 hours of student effort per week per credit point for units of study offered over a full semester. For a 6 credit point unit, this equates to roughly 120-150 hours of student effort in total.

Learning outcomes

Learning outcomes are what students know, understand and are able to do on completion of a unit of study. They are aligned with the University's graduate qualities and are assessed as part of the curriculum.

At the completion of this unit, you should be able to:

LO1. Understand and plan for the process of incremental implementation, recognising the importance of project management, teamwork, software/hardware co-design, and iterative development by members of a development team.
LO2. Design and prototype the hardware and software.
LO3. Understand in detail the software and hardware architecture of a modern digital programming.
LO4. Understand the basic architecture of traditional and modern FPGAs and System-on-Chips (SoCs)
LO5. Understand engineering concepts in the design of digital circuits.
LO6. Understand the role of hardware description languages in digital circuit implementation and describe simple hardware functions using a hardware description language.
LO7. Demonstrate the ability to differentiate between CISC, RISC, DSP processors and FPGAs, understanding the reasons for their evolution and adoption in specific designs.
LO8. Understand and select appropriately between various alternatives for data communications within a mechatronic system.

Graduate qualities

The graduate qualities are the qualities and skills that all University of Sydney graduates must demonstrate on successful completion of an award course. As a future Sydney graduate, the set of qualities have been designed to equip you for the contemporary world.

GQ1	Depth of disciplinary expertise Deep disciplinary expertise is the ability to integrate and rigorously apply knowledge, understanding and skills of a recognised discipline defined by scholarly activity, as well as familiarity with evolving practice of the discipline.
GQ2	Critical thinking and problem solving Critical thinking and problem solving are the questioning of ideas, evidence and assumptions in order to propose and evaluate hypotheses or alternative arguments before formulating a conclusion or a solution to an identified problem.
GQ3	Oral and written communication Effective communication, in both oral and written form, is the clear exchange of meaning in a manner that is appropriate to audience and context.
GQ4	Information and digital literacy Information and digital literacy is the ability to locate, interpret, evaluate, manage, adapt, integrate, create and convey information using appropriate resources, tools and strategies.
GQ5	Inventiveness Generating novel ideas and solutions.
GQ6	Cultural competence Cultural Competence is the ability to actively, ethically, respectfully, and successfully engage across and between cultures. In the Australian context, this includes and celebrates Aboriginal and Torres Strait Islander cultures, knowledge systems, and a mature understanding of contemporary issues.
GQ7	Interdisciplinary effectiveness Interdisciplinary effectiveness is the integration and synthesis of multiple viewpoints and practices, working effectively across disciplinary boundaries.
GQ8	Integrated professional, ethical, and personal identity An integrated professional, ethical and personal identity is understanding the interaction between one’s personal and professional selves in an ethical context.
GQ9	Influence Engaging others in a process, idea or vision.

Outcome map

Learning outcomes	Graduate qualities
Learning outcomes

Alignment with Competency standards

Outcomes	Competency standards
	National Standard of Competency for Architects - 1. Design: Project briefing 2. Design: Pre-Design 4. Design: Schematic Design

Responding to student feedback

This section outlines changes made to this unit following staff and student reviews.

The course has been restructured to include modern embedded systems design updating the hardware and the course content.

Additional information

Work, health and safety

In response to the COVID-19 pandemic lectures will be delivered via a combination of videos, Zoom and in-person sessions. In-person attendance at lab sessions is preferred, but arrangements will be made for remote students.

For those attending labs in person, we have made some adjustments to how the Mechatronics Lab is managed:

You will only have access to the lab during your scheduled lab sessions.
A record of attendance will be kept for contact tracing if required.
We have limited student numbers in each lab session to allow this physical distancing to be maintained.
The use of hand sanitiser and disinfectant wipes before and after using Lab facilities is mandatory.
Personal protective equipment (PPE) in the form of face masks is strongly recommended. Please acquire face masks and bring them to all your classes in the Mechatronics Lab starting from Week 1.
Obey all Lab signage including guidelines for sanitising workstations and hardware, PPE, and procedures for entry and exit.
If you are feeling unwell, please stay at home.

The COVID situation is still evolving: please monitor email closely for any changes in policy.

Disclaimer

The University reserves the right to amend units of study or no longer offer certain units, including where there are low enrolment numbers.

To help you understand common terms that we use at the University, we offer an online glossary.

Current students

Overview

Overview

Unit details and rules

Teaching staff

Assessment

Assessment

Assessment summary

Assessment criteria

Late submission

Academic integrity

Learning support

Learning support

Simple extensions

Special consideration

Using AI responsibly

Weekly schedule

Weekly schedule

Study commitment

Learning outcomes

Learning outcomes

Graduate qualities

Outcome map

Alignment with Competency standards

Responding to student feedback

Responding to student feedback

Additional information

Additional information

Work, health and safety

Disclaimer

On this page

Useful links

Media

Student links

About us

Connect

Current students

MTRX3700: Mechatronics 3

Semester 2, 2023 [Normal day] - Camperdown/Darlington, Sydney

Overview

Overview

Unit details and rules

Teaching staff

Assessment

Assessment

Assessment summary

Assessment criteria

Late submission

Academic integrity

Learning support

Learning support

Simple extensions

Special consideration

Using AI responsibly

Weekly schedule

Weekly schedule

Study commitment

Learning outcomes

Learning outcomes

Graduate qualities

Outcome map

Alignment with Competency standards

Responding to student feedback

Responding to student feedback

Additional information

Additional information

Work, health and safety

Disclaimer

On this page

Useful links

Media

Student links

About us

Connect