ELEC9602: Semester 1, 2023

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Units ELEC9602 Semester 1 2023 [Normal day]

Unit of study_

ELEC9602: Digital Logic

Overview

The purpose of this unit is to equip students with the skills to design simple digital logic circuits which comprise modules of larger digital systems. The following topics are covered: logic operations, theorems and Boolean algebra, number systems (integer and floating point), combinational logic analysis and synthesis, sequential logic, registers, counters, bus systems, state machines, simple CAD tools for logic design, and the design of a simple computer.

Details

Academic unit	Electrical and Information Engineering
Unit code	ELEC9602
Unit name	Digital Logic
Session, year ?	Semester 1, 2023
Attendance mode	Normal day
Location	Remote
Credit points	6

Enrolment rules

Prohibitions ?	ELEC5722
Prerequisites ?	None
Corequisites ?	None
Assumed knowledge ?	This unit of study assumes some knowledge of digital data representation and basic computer organisation
Available to study abroad and exchange students	No

Teaching staff and contact details

Coordinator	David Boland, david.boland@sydney.edu.au
Laboratory supervisor(s)	Thomas Huang , thomas.huang@sydney.edu.au
Laboratory supervisor(s)	Peter Jones, peter.jones@sydney.edu.au
Lecturer(s)	David Boland , david.boland@sydney.edu.au

Type	Description	Weight	Due	Length
Supervised exam ?	Final exam Verilog (modelsim/verilator) design activity based on labs/project.	40%	Formal exam period	2 hours
Outcomes assessed:
Assignment	Lab exercises Completion of lab exercises as groups is marked. (Sparkplus)	12.5%	Multiple weeks	n/a
Outcomes assessed:
Assignment	Lab project Verilog design exercise as a group. Assessment in Week 13 lab session.	27.5%	Multiple weeks	n/a
Outcomes assessed:
Small test	Combinational Logic Quiz Canvas Quiz (open book)	10%	Week 07	50 minutes
Outcomes assessed:
Small test	Sequential Logic and Timing Quiz Canvas Quiz (open book)	10%	Week 13	50 minutes
Outcomes assessed:
= group assignment ?

Lab exercises: Total of 6 lab exercises, with 5 lab exercises assessed during lab sessions based on demonstrated work and understanding. Completed in groups and assessed individually.
Lab project: Major project running over 3 weeks, assessed during lab sessions based on demonstrated work and lab report. Completed in groups and assessed individually.
Final exam: Two hours during formal exam period.

Detailed information for each assessment can be found on Canvas.

Assessment criteria

The University awards common result grades, set out in the Coursework Policy 2014 (Schedule 1).

As a general guide, a high distinction indicates work of an exceptional standard, a distinction a very high standard, a credit a good standard, and a pass an acceptable standard.

Result name	Mark range	Description
High distinction	85 - 100
Distinction	75 - 84
Credit	65 - 74
Pass	50 - 64
Fail	0 - 49	When you don’t meet the learning outcomes of the unit to a satisfactory standard.

For more information see sydney.edu.au/students/guide-to-grades.

Late submission

In accordance with University policy, these penalties apply when written work is submitted after 11:59pm on the due date:

Deduction of 5% of the maximum mark for each calendar day after the due date.
After ten calendar days late, a mark of zero will be awarded.

Special consideration

If you experience short-term circumstances beyond your control, such as illness, injury or misadventure or if you have essential commitments which impact your preparation or performance in an assessment, you may be eligible for special consideration or special arrangements.

Academic integrity

The Current Student website provides information on academic integrity and the resources available to all students. The University expects students and staff to act ethically and honestly and will treat all allegations of academic integrity breaches seriously.

We use similarity detection software to detect potential instances of plagiarism or other forms of academic integrity breach. If such matches indicate evidence of plagiarism or other forms of academic integrity breaches, your teacher is required to report your work for further investigation.

You may only use artificial intelligence and writing assistance tools in assessment tasks if you are permitted to by your unit coordinator, and if you do use them, you must also acknowledge this in your work, either in a footnote or an acknowledgement section.

Studiosity is permitted for postgraduate units unless otherwise indicated by the unit coordinator. The use of this service must be acknowledged in your submission.

Weekly schedule

WK	Topic	Learning activity
Week 01	Introduction to digital logic	Lecture (2 hr)
Week 02	VHDL and implementing logic functions	Lecture and tutorial (5 hr)
Week 03	Combinational building blocks and VHDL	Lecture and tutorial (5 hr)
Week 04	VHDL building blocks, numbers and adders	Lecture and tutorial (5 hr)
Week 05	Comparators, adders and subtractors	Lecture and tutorial (5 hr)
Week 06	Flip-flops, latches and clocks	Lecture and tutorial (5 hr)
Week 07	Registers and counters	Lecture and tutorial (5 hr)
Week 08	Finite state machines	Lecture and tutorial (5 hr)
Week 09	Datapaths and control	Lecture and tutorial (5 hr)
Week 10	Processors, memory and branching	Lecture and tutorial (5 hr)
Week 11	Multipliers, dividers and timing	Lecture and tutorial (5 hr)
Week 12	Metastability and reconfigurable logic	Lecture and tutorial (5 hr)
Week 13	Synthesis, testing and exam review	Lecture and tutorial (5 hr)

Study commitment

Typically, there is a minimum expectation of 1.5-2 hours of student effort per week per credit point for units of study offered over a full semester. For a 6 credit point unit, this equates to roughly 120-150 hours of student effort in total.

Required readings

All readings for this unit can be accessed through the Library eReserve, available on Canvas.

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design (3rd). McGraw-Hill, 2009. 978-0-07-352953-0

Learning outcomes

Learning outcomes are what students know, understand and are able to do on completion of a unit of study. They are aligned with the University’s graduate qualities and are assessed as part of the curriculum.

Outcomes
Graduate qualities

At the completion of this unit, you should be able to:

LO1. design, fabricate and test the digital circuits and system in the laboratory
LO2. design combinational and sequential circuits and systems, using a clearly defined system based approach
LO3. understand how Boolean Algebrea can be used for the purpose of logic circuit analysis
LO4. describe basic digital logic building blocks such as logic gates, multiplexers, decoders, and PLAs
LO5. discuss how sequential logic components such as latches, flip-flops, registers and counters work
LO6. evaluate the performance of clocked sequential circuits
LO7. communicate effectively among the team members of the group.

Graduate qualities

The graduate qualities are the qualities and skills that all University of Sydney graduates must demonstrate on successful completion of an award course. As a future Sydney graduate, the set of qualities have been designed to equip you for the contemporary world.

GQ1	Depth of disciplinary expertise Deep disciplinary expertise is the ability to integrate and rigorously apply knowledge, understanding and skills of a recognised discipline defined by scholarly activity, as well as familiarity with evolving practice of the discipline.
GQ2	Critical thinking and problem solving Critical thinking and problem solving are the questioning of ideas, evidence and assumptions in order to propose and evaluate hypotheses or alternative arguments before formulating a conclusion or a solution to an identified problem.
GQ3	Oral and written communication Effective communication, in both oral and written form, is the clear exchange of meaning in a manner that is appropriate to audience and context.
GQ4	Information and digital literacy Information and digital literacy is the ability to locate, interpret, evaluate, manage, adapt, integrate, create and convey information using appropriate resources, tools and strategies.
GQ5	Inventiveness Generating novel ideas and solutions.
GQ6	Cultural competence Cultural Competence is the ability to actively, ethically, respectfully, and successfully engage across and between cultures. In the Australian context, this includes and celebrates Aboriginal and Torres Strait Islander cultures, knowledge systems, and a mature understanding of contemporary issues.
GQ7	Interdisciplinary effectiveness Interdisciplinary effectiveness is the integration and synthesis of multiple viewpoints and practices, working effectively across disciplinary boundaries.
GQ8	Integrated professional, ethical, and personal identity An integrated professional, ethical and personal identity is understanding the interaction between one’s personal and professional selves in an ethical context.
GQ9	Influence Engaging others in a process, idea or vision.

Outcome map

Learning outcomes	Graduate qualities
Learning outcomes

Closing the loop

We are modifying labs and lectures for some more Introduction to Verilog content.

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Current students

Overview

Details

Enrolment rules

Teaching staff and contact details

Assessment

Assessment criteria

Late submission

Special consideration

Academic integrity

Weekly schedule

Study commitment

Required readings

Learning outcomes

Graduate qualities

Outcome map

Closing the loop

Disclaimer

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