Skip to main content
Unit of study_

MTRX3700: Mechatronics 3

Semester 2, 2022 [Normal day] - Remote

This unit of study aims to provide experience, confidence and competence in the design and implementation of embedded systems; to impart a detailed knowledge of the software and hardware architecture of modern embedded systems and an understanding of the use of these resources in product design; and to provide experience of working in a project team to design and prototype an embedded system. Content will include single processor systems, multiple and distributed processing systems, special purpose architectures (FPGA, DSPs etc) and their applications; embedded operating systems; standard interfacing of sensor and actuation systems; ADC/DAC, SSI, parallel, CAN bus etc.; specific requirements for embedded systems; problem definition and system design; tools for design, development and testing of prototype systems. The unit of study will include a project where groups of students design, develop and commission an embedded system product to meet a specification. At the end of this unit students will understand the organisation of single and multiple processor systems, special purpose architectures (FPGAs, DSPs etc.) and their applications. Students will have a detailed knowledge of the software and hardware architecture of a modern embedded system. This knowledge will include an in-depth understanding of the advantages and limitations of embedded processors, of the utilisation and interfacing of hardware resources, and of the design and development of software for embedded applications. The students will have the competence to develop and prototype embedded systems.

Unit details and rules

Unit code MTRX3700
Academic unit Aerospace, Mechanical and Mechatronic
Credit points 6
Assumed knowledge

Completion of a first course in microprocessor systems, including assembly and C language programming, interfacing, introductory digital and analogue electronics

Available to study abroad and exchange students


Teaching staff

Coordinator Viorela Ila,
Lecturer(s) Viorela Ila,
Tutor(s) Steven Liu,
Lewis Watts,
Khit Nay,
Type Description Weight Due Length
Final exam (Open book) Type C final exam hurdle task Final Exam
Open book (Type C).
30% Formal exam period 2 hours
Outcomes assessed: LO3 LO2 LO4 LO5 LO6 LO7 LO8
Assignment group assignment Assignment 4: Major Project
Assessment will include a pitch (10%), demo (50%), report (30%), Q&A(10%).
Due date: 13 Nov 2022 at 23:59
4 weeks
Outcomes assessed: LO1 LO2 LO3 LO4 LO5 LO6 LO7 LO8
Assignment group assignment Assignment 1: Microcontroller lab practice
Assessment will include in-class demonstrations and a report.
20% Week 04
Due date: 28 Aug 2022 at 23:59
4 weeks
Outcomes assessed: LO1 LO2 LO3
Assignment group assignment Assignment 2: FPGA environment setup
Assessment will include in-class demonstrations.
5% Week 06
Due date: 08 Sep 2022 at 18:00
2 weeks
Outcomes assessed: LO3
Assignment group assignment Assignment 3: FPGA programming
Assessment will include in-class demonstrations and a report.
15% Week 09
Due date: 09 Oct 2022 at 23:59
3 weeks
Outcomes assessed: LO1 LO4 LO5 LO6
hurdle task = hurdle task ?
group assignment = group assignment ?
Group assignment with individually assessed component = group assignment with individually assessed component ?
Type C final exam = Type C final exam ?

Assessment summary

Assessment Description

  • Assignment 1: Microcontroller lab practice: Students will be working in small groups and is intended to ensure that all students gain advance microcontroller programming knowledge.
  • Assignemnt 2: Setup FPGA Environment: Students will be working in small groups and will setup their FPGA programming environment.
  • Assignemnt 3: FPGA Programming: Students ill be working in small groups to  develop an FPGA programming project.
  • Assignemnt 4: Major Project: MTRX3700 Mechatronics 3 is a project-based unit of study. Students will work in larger groups of 6-7. There is strong emphasis placed on understanding the material so that a student can make things work in the lab. Most of the learning will therefore occur in the laboratory, and the assessment weighting of assignment and project work reflects this.
  • Demonstration: All assignments and the major project will have a mandatory in-lab demonstration component during the last weeek of each assignment
  • Presentation: An oral presentation is required early in the Major Project development cycle. The intent is to simulate a typical step in product development, where a team must rapidly be formed, responsibilities allocated, project planning commenced and a preliminary design presented to the client.
  • Q&A:  After demonstrating the Assignment 1 and the Major Project, each student will individualy answer questions related to the implementation.
  • Moderation of Group Work Marks: Group marks for Lab Work will be moderated on the basis of individual effort and understanding, as perceived by the Lecturer and Tutor(s) and as self-reported by group members.
  • Must Pass Exams: To pass this unit of study it is necessary to obtain a mark of not less than 45% in the Examination component.
  • Detailed information for each assessment task can be found on Canvas.

Assessment Feedback

  • Students can expect feedback for this Unit of Study through discussion during lectures and laboratory sessions, through participation in the Ed discussion forum, and through written comments on assignments.
  • Students can provide feedback to the Lecturers and Tutors by discussion during lectures or tutorial/ laboratory sessions, and by submitting comments and questions to the Ed discussion forum.

Assessment criteria

The University awards common result grades as set out in the Coursework Policy 2014 (Schedule 1).

Standards Based Assessment

Final grades in this unit are awarded at levels of HD for High Distinction, DI for Distinction, CR for Credit, PS for Pass and FA for Fail as defined by University of Sydney Coursework Policy 2014.

As a general guide, a high distinction indicates work of an exceptional standard, a distinction a very high standard, a credit a good standard, and a pass an acceptable standard. For more information see


For more information see guide to grades.

Late submission

In accordance with University policy, these penalties apply when written work is submitted after 11:59pm on the due date:

  • Deduction of 5% of the maximum mark for each calendar day after the due date.
  • After ten calendar days late, a mark of zero will be awarded.

Academic integrity

The Current Student website  provides information on academic integrity and the resources available to all students. The University expects students and staff to act ethically and honestly and will treat all allegations of academic integrity breaches seriously.  

We use similarity detection software to detect potential instances of plagiarism or other forms of academic integrity breach. If such matches indicate evidence of plagiarism or other forms of academic integrity breaches, your teacher is required to report your work for further investigation.

You may only use artificial intelligence and writing assistance tools in assessment tasks if you are permitted to by your unit coordinator, and if you do use them, you must also acknowledge this in your work, either in a footnote or an acknowledgement section.

Studiosity is permitted for postgraduate units unless otherwise indicated by the unit coordinator. The use of this service must be acknowledged in your submission.

Simple extensions

If you encounter a problem submitting your work on time, you may be able to apply for an extension of five calendar days through a simple extension.  The application process will be different depending on the type of assessment and extensions cannot be granted for some assessment types like exams.

Special consideration

If exceptional circumstances mean you can’t complete an assessment, you need consideration for a longer period of time, or if you have essential commitments which impact your performance in an assessment, you may be eligible for special consideration or special arrangements.

Special consideration applications will not be affected by a simple extension application.

Using AI responsibly

Co-created with students, AI in Education includes lots of helpful examples of how students use generative AI tools to support their learning. It explains how generative AI works, the different tools available and how to use them responsibly and productively.

WK Topic Learning activity Learning outcomes
Multiple weeks Students are expected to commit to at least 5 hours per week of independent study in addition to timetabled activities. Independent study (60 hr) LO1 LO2 LO3 LO4 LO5 LO6 LO7 LO8
Week 01 Introduction, hardware overview, IDE Lecture (3 hr) LO2 LO3
Microcontroller lab practice Computer laboratory (3 hr) LO1 LO2 LO3 LO8
Week 02 Hardware architecture: I/O, ADC, IMU, WIFI,BLE Lecture (3 hr) LO2 LO3 LO8
Microcontroller lab practice Computer laboratory (3 hr) LO1 LO2 LO3 LO8
Week 03 Communication 1: UART, SPI, I2C, TCP/IP Lecture (3 hr) LO2 LO3 LO8
Microcontroller lab practice Computer laboratory (3 hr) LO1 LO2 LO3 LO8
Week 04 Communication 2: Bluetooth, BLE Lecture (3 hr) LO2 LO3 LO8
Microcontroller lab practice Computer laboratory (3 hr) LO1 LO2 LO3 LO8
Week 05 Introduction to FPGA architecture Lecture (3 hr) LO4 LO5 LO7
Setup FPGA environment Computer laboratory (3 hr) LO1 LO6
Week 06 Introduction to hardware description language Lecture (3 hr) LO4 LO5 LO6
Setup FPGA environment Computer laboratory (3 hr) LO1 LO4 LO5 LO6
Week 07 Digital logic simulation and debug Lecture (2 hr) LO4 LO5 LO6
FPGA programming Computer laboratory (3 hr) LO1 LO4 LO5 LO6
Week 08 FPGA design Lecture (2 hr) LO4 LO5 LO6 LO7
FPGA programming Computer laboratory (3 hr) LO1 LO4 LO5 LO6
Week 09 System Design, SoC, soft Processor Lecture (3 hr) LO4 LO5 LO6
FPGA programming Computer laboratory (3 hr) LO1 LO4 LO5 LO6
Week 10 Hardware/Software codesign Lecture (3 hr) LO4 LO5 LO6 LO7 LO8
Group work on the Major Project Project (3 hr) LO1 LO2 LO3 LO4 LO5 LO6 LO8
Week 11 RISC processors and DSPs Lecture (2 hr) LO7
Group work on the Major Project Project (3 hr) LO1 LO2 LO3 LO4 LO5 LO6 LO8
Week 12 Overview Lecture (2 hr) LO3 LO4 LO7 LO8
Group work on the Major Project Project (3 hr) LO1 LO2 LO3 LO4 LO5 LO6 LO8
Week 13 Major Project evaluation Project (3 hr) LO1 LO2 LO3 LO4 LO5 LO6 LO8

Study commitment

Typically, there is a minimum expectation of 1.5-2 hours of student effort per week per credit point for units of study offered over a full semester. For a 6 credit point unit, this equates to roughly 120-150 hours of student effort in total.

Learning outcomes are what students know, understand and are able to do on completion of a unit of study. They are aligned with the University's graduate qualities and are assessed as part of the curriculum.

At the completion of this unit, you should be able to:

  • LO1. Understand and plan for the process of incremental implementation, recognising the importance of project management, teamwork, software/hardware co-design, and iterative development by members of a development team.
  • LO2. Design and prototype the hardware and software comprising a microcontroller-based system.
  • LO3. Understand in detail the software and hardware architecture of a modern microcontroller, including the relationship between high-level language (C) and the hardware, the utilisation and interfacing of microcontroller hardware resources, and the design and development of software.
  • LO4. Understand the basic architecture of traditional and modern FPGAs and System-on-Chips (SoCs)
  • LO5. Understand engineering concepts in the design of digital circuits.
  • LO6. Understand the role of hardware description languages in digital circuit implementation and describe simple hardware functions using a hardware description language.
  • LO7. Demonstrate the ability to differentiate between CISC, RISC, DSP processors and FPGAs, understanding the reasons for their evolution and adoption in specific designs.
  • LO8. Understand and select appropriately between various alternatives for data communications within a mechatronic system.

Graduate qualities

The graduate qualities are the qualities and skills that all University of Sydney graduates must demonstrate on successful completion of an award course. As a future Sydney graduate, the set of qualities have been designed to equip you for the contemporary world.

GQ1 Depth of disciplinary expertise

Deep disciplinary expertise is the ability to integrate and rigorously apply knowledge, understanding and skills of a recognised discipline defined by scholarly activity, as well as familiarity with evolving practice of the discipline.

GQ2 Critical thinking and problem solving

Critical thinking and problem solving are the questioning of ideas, evidence and assumptions in order to propose and evaluate hypotheses or alternative arguments before formulating a conclusion or a solution to an identified problem.

GQ3 Oral and written communication

Effective communication, in both oral and written form, is the clear exchange of meaning in a manner that is appropriate to audience and context.

GQ4 Information and digital literacy

Information and digital literacy is the ability to locate, interpret, evaluate, manage, adapt, integrate, create and convey information using appropriate resources, tools and strategies.

GQ5 Inventiveness

Generating novel ideas and solutions.

GQ6 Cultural competence

Cultural Competence is the ability to actively, ethically, respectfully, and successfully engage across and between cultures. In the Australian context, this includes and celebrates Aboriginal and Torres Strait Islander cultures, knowledge systems, and a mature understanding of contemporary issues.

GQ7 Interdisciplinary effectiveness

Interdisciplinary effectiveness is the integration and synthesis of multiple viewpoints and practices, working effectively across disciplinary boundaries.

GQ8 Integrated professional, ethical, and personal identity

An integrated professional, ethical and personal identity is understanding the interaction between one’s personal and professional selves in an ethical context.

GQ9 Influence

Engaging others in a process, idea or vision.

Outcome map

Learning outcomes Graduate qualities

Alignment with Competency standards

Outcomes Competency standards
National Standard of Competency for Architects - AACA
1. Design: Project briefing
2. Design: Pre-Design
4. Design: Schematic Design

This section outlines changes made to this unit following staff and student reviews.

The course has been restructured to include modern embedded systems design updating the hardware and the course content.

Work, health and safety

In response to the COVID-19 pandemic lectures will be delivered via a combination of videos, Zoom and in-person sessions. In-person attendance at lab sessions is preferred, but arrangements will be made for remote students.

For those attending labs in person, we have made some adjustments to how the Mechatronics Lab is managed:

  • You will only have access to the lab during your scheduled lab sessions.
  • A record of attendance will be kept for contact tracing if required.
  • We have limited student numbers in each lab session to allow this physical distancing to be maintained.
  • The use of hand sanitiser and disinfectant wipes before and after using Lab facilities is mandatory.
  • Personal protective equipment (PPE) in the form of face masks is strongly recommended. Please acquire face masks and bring them to all your classes in the Mechatronics Lab starting from Week 1.
  • Obey all Lab signage including guidelines for sanitising workstations and hardware, PPE, and procedures for entry and exit.
  • If you are feeling unwell, please stay at home.

The COVID situation is still evolving: please monitor email closely for any changes in policy.


The University reserves the right to amend units of study or no longer offer certain units, including where there are low enrolment numbers.

To help you understand common terms that we use at the University, we offer an online glossary.